Search for: All records

High contact resistance is one of the primary concerns for electronic device applications of two-dimensional (2D) layered semiconductors. Here, we explore the enhanced carrier transport through metal–semiconductor interfaces in WS 2 field effect transistors (FETs) by introducing a typical transition metal, Cu, with two different doping strategies: (i) a “generalized” Cu doping by using randomly distributed Cu atoms along the channel and (ii) a “localized” Cu doping by adapting an ultrathin Cu layer at the metal–semiconductor interface. Compared to the pristine WS 2 FETs, both the generalized Cu atomic dopant and localized Cu contact decoration can provide a Schottky-to-Ohmic contact transition owing to the reduced contact resistances by 1–3 orders of magnitude, and consequently elevate electron mobilities by 5–7 times. Our work demonstrates that the introduction of transition metal can be an efficient and reliable technique to enhance the carrier transport and device performance in 2D TMD FETs. 

Abstract 2D semiconductors such as monolayer molybdenum disulfide (MoS₂) are promising material candidates for next‐generation nanoelectronics. However, there are fundamental challenges related to their metal–semiconductor (MS) contacts, which limit the performance potential for practical device applications. In this work, 2D monolayer hexagonal boron nitride (h‐BN) is exploited as an ultrathin decorating layer to form a metal–insulator–semiconductor (MIS) contact, and an innovative device architecture is designed as a platform to reveal a novel diode‐like selective enhancement of the carrier transport through the MIS contact. The contact resistance is significantly reduced when the electrons are transported from the semiconductor to the metal, but is barely affected when the electrons are transported oppositely. A concept of carrier collection barrier is proposed to interpret this intriguing phenomenon as well as a negative Schottky barrier height obtained from temperature‐dependent measurements, and the critical role of the collection barrier at the drain end is shown for the overall transistor performance.